This document presents design techniques and reference circuits that power Virtex™-4 FXRocketIO™ multi-gigabit transceivers (MGTs) operating at data rates below 3.125 Gb/s.When using multiple transceivers, it is sometimes preferred to power them from a switchingpower supply. However, switching power supplies generate noise that affects transceiver
上传时间： 2013-11-18
上传用户：huang111
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
上传时间： 2014-12-05
上传用户：flg0001
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
上传时间： 2015-01-02
上传用户：JIUSHICHEN
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
上传时间： 2013-12-25
上传用户：jkhjkh1982
This the 8th release of PicoBlaze for Spartan-3, Spartan-3E Virtex-II, Virtex-IIPro and Virtex-4 devices by Picoblaze
标签： Spartan Virtex-IIPro PicoBlaze Virtex-II
上传时间： 2016-02-08
上传用户：cccole0605
Xilinx Virtex 4 ML405开发平台的原理图 设置引脚文件的时候可以用到
上传时间： 2013-11-30
上传用户：AbuGe
xilinx Virtex-4 fpga开发板（ML402,ML403等）的使用入门手册
上传时间： 2013-12-26
上传用户：mpquest
这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。
上传时间： 2017-05-20
上传用户：llandlu
EDK 9.1 MicroBlaze Tutorial in Virtex-4
标签： MicroBlaze Tutorial Virtex EDK
上传时间： 2013-11-26
上传用户：xiaodu1124
This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to set up a simple EDK Base System Builder system on the ML405Evaluation Platform and run performance tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 Evaluation Platform. The instructions forobtaining and setting up the software used to perform the measurements, netperf, are given.
上传时间： 2013-11-11
上传用户：saharawalker
